Field programmable gate array including a nonvolatile user memory and method for programming

ABSTRACT

An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of co-pending U.S. patent applicationSer. No. 11/336,396, filed Jan. 20, 2006, which claims priority fromU.S. Provisional Patent application Ser. No. 60/645,998, filed Jan. 21,2005, which are hereby incorporated by reference as if set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to Field Programmable Gate Arrays (FPGAs). Moreparticularly, this invention relates to a Field Programmable Gate Arrayhaving a non-volatile user memory. Still more particularly, thisinvention relates to configuring an FPGA and storing data in thenon-volatile user memory in the FPGA.

2. Background

Programmable logic devices are known in the art. Programmable logicdevices include complex programmable logic device (CPLD),Field-programmable gate array (FPGA), and other configurable integratedcircuits known in the art. An FPGA is the most complex type ofprogrammable logic device, comprising any number of logic modules, aninterconnect-routing architecture and programmable elements that may beprogrammed to selectively interconnect the logic modules to one anotherand to define the functions of the logic modules. To implement aparticular circuit function, the circuit is mapped into the array andthe appropriate programmable elements are programmed to implement thenecessary wiring connections that form the user circuit.

An FPGA includes an array of general-purpose logic circuits, calledcells or logic blocks, whose functions are programmable. Programmablerouting lines link the cells to one another. The cell types may be smallmultifunction circuits (or configurable functional blocks or groups)capable of realizing Boolean functions of multiple variables. The celltypes are not restricted to gates. For example, configurable functionalgroups typically include memory cells and connection transistors thatmay be used to configure logic functions such as addition, subtraction,etc., inside of the FPGA. A cell may also contain a plurality offlip-flops. Two types of logic cells found in FPGA devices are thosebased on multiplexers and those based on programmable read only memory(PROM) table-lookup memories. Erasable FPGAs can be reprogrammed manytimes. This technology is especially convenient when developing anddebugging a prototype design for a new product and for small-scalemanufacture.

An FPGA circuit can be programmed to implement virtually any set ofdigital functions. Input signals are processed by the programmed circuitto produce the desired set of outputs. Such inputs flow from the user'ssystem, through input buffers and through the circuit, and finally backout the user's system via output buffers referred to as input/outputports (I/Os). Such buffers provide any or all of the followinginput/output (I/O) functions: voltage gain, current gain, leveltranslation, delay, signal isolation, and hysteresis. The input/outputports provide the access points for communication between chips. I/Oports vary in complexity depending on the FPGA.

FPGAs may be customized by a user to perform a wide variety ofcombinatorial and sequential logic functions. Numerous architectures forsuch integrated circuits are known. Examples of such architectures arefound disclosed in U.S. Pat. No. 4,870,302 to Freeman, U.S. Pat. No.4,758,745 to El Gamal et al., and U.S. Pat. No. 5,132,571 to McCollum etal., as well as many others. The architecture employed in a particularFPGA integrated circuit will determine the richness and density of thepossible interconnections that can be made among the various circuitelements disposed on the integrated circuit and thus profoundly affectits usefulness.

Non-volatile memories, such as flash memories are known in the art.Flash memories are electrically erasable and are generally used to storedata where it is undesirable that the data be lost when the device isnot connected to a power source. Non-volatile memories are often used tostore the configuration data for FPGAs such as SRAM FPGAs that are basedon volatile technology. Configuration data may be loaded from a flashmemory into an SRAM-based FPGA each time the FPGA is powered up. Otherflash memory devices are used in systems to store user data. User datais data generated or used in the operation of an FPGA device, as opposedto configuration data which is used to configure the programmable logicand routing to define the function of the FPGA.

Programmable logic devices available from Lattice SemiconductorCorporation, Hillsboro, Oreg. and Altera Corporation, San Jose, Calif.use on-chip blocks of flash memory to load and control SRAM programmableelements in single chips. For example, the ispXP (eXpandedProgrammability) product available from Lattice Semiconductor combineselectrically-erasable—programmable-read-only memory (EEPROM) and SRAMtechnologies. These types of programmable logic devices add an advantageof not needing a separate non-volatile memory chip, but the SRAMprogrammable logic configuration still has to be loaded from thenon-volatile memory block during power-up.

An example of a semiconductor device 700 employing on-board non-volatilememory to load configuration data into an SRAM programmable logic unit702 is shown in FIG. 1. Non-volatile EEPROM array 50 stores the deviceconfiguration. At power-up, this information is transferred in aparallel fashion into SRAM cells 704 in the programmable logic unit 702.The loading of the configuration data from the non-volatile memory 50into the SRAM programmable logic 702 may be performed under the controlof control logic 720. JTAG port 730 and system configuration port 740allow for in-system programming.

Field Programmable Gate Arrays (FPGAs) including volatile memories thatare available to store user data are known in the art. SRAM-based FPGAssuch as those, for example, available from Xilinx Corporation, San Jose,Calif. include SRAM-based volatile memory blocks. Some of these blocksmay be available for user data. Even on non-volatile FPGAs, however,such as antifuse—based FPGAs, the memory blocks are volatile (generallySRAM-based). Prior art FPGAs do not, therefore include on-chipnon-volatile memories available for storing user data.

It is a problem in FPGAs containing volatile logic and memory that theFPGA must be programmed each time the device is powered up. Thus, theconfiguration data and any user data must be stored in a memory outsidethe FPGA. Thus, power up of the FPGA is slow and requires an excessiveamount of power in order to receive configuration and user data over theInput/Output (I/O) of the FPGA.

Furthermore, since all the configuration memory and user data must beloaded using the I/O of the FPGA, security of the data is a problem.Security is a problem because the wires connecting the I/O of the FPGAto the system loading the data may be easily tapped. Thus, those skilledin the art are continually looking for ways to provide an FPGA thatprovides a fast, secure, power up with relatively low power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified block diagram of a prior art programmablelogic device including an on-chip non-volatile memory.

FIG. 2 shows a simplified block diagram of a portion of an FPGAincluding an on-chip non-volatile memory, in accordance with anembodiment of the present invention.

FIG. 3 shows a simplified block diagram of an FPGA including an on-chipuser-accessible non-volatile memory, in accordance with an embodiment ofthe present invention.

FIG. 4 shows a simplified block diagram of a system including an FPGAwith an on-chip user-accessible non-volatile memory, in accordance withan embodiment of the present invention.

FIG. 5 shows a flow diagram of a method for programming an FPGAincluding a user-accessible non-volatile memory, in accordance with anembodiment of the present invention.

FIG. 6 shows a flow diagram of a method for reading an FPGA including auser-accessible non-volatile memory, in accordance with an embodiment ofthe present invention.

FIG. 7 shows a flow diagram of a method for controlling access to aportion of a non-volatile memory on an FPGA, in accordance with anembodiment of the present invention.

DETAILED DESCRIPTION

This invention relates to a system and method for programming a FieldProgrammable Gate Array (FPGA) that includes a non-volatile memory. Anadvantage of the present invention is that configuration data and userdata may be loaded at one time into the FPGA. Thus, the configurationdata and user data do not need to be loaded at each power up. Thisreduces the time and power required for power up of the FPGA. Since theconfiguration data and user data are not required to be loaded at eachpower up, security of the FPGA data is improved. Portions of the memorymay be designated as read-only and may not be subsequently erased orover-written.

In order to provide a non-volatile memory in the FPGA, the memory may bea flash memory and the circuitry of the FPGA may be configured fromfloating gate transistors. Alternatively, the programmable logic cellsfor the FPGA and the non-volatile memory may be based on othernon-volatile transistors known in the art such as, for example, SONOS,MONOS, silicon nanocrystal, ferro-electric, and solid-electrolyteswitching devices, and other types as will be appreciated by persons ofordinary skill in the art. In accordance with this invention, aprogramming system programs an FPGA having a non-volatile memory in thefollowing manner. The system receives configuration data for programmingthe non-volatile FPGA and user data to be stored in the non-volatileuser memory of the FPGA. Security data for the FPGA may also be receivedby the system and stored in the non-volatile memory of the FPGA.

In some embodiments of the invention, the user data and security datamay be stored in a system memory used to load the FPGA, The system maygenerate a programming file, for example a STAPL file, which may includethe including security data, configuration data, and user data to beprogrammed into the programmable logic unit and the non-volatile memorythen used to load the configuration data and the user data to thenon-volatile memory in the FPGA.

In some embodiments in accordance with this invention, the non-volatilememory may be programmed with specific device data and device type data.Specific device data is data that pertains to the particular FPGA. Someexamples of specific device data include a device serial number, a datestamp, and an identifier. The device type data is data that pertains toa particular family or product line of FPGAs. Some examples of devicetype data may include a product identifier code, parameters for aparticular function, and values of constants for certain applicationsperformed by the FPGA. The system may read device type data from a firstportion of a system memory and the specific device data from anotherportion of the system memory.

In some embodiments in accordance with this invention, the system mayreceive an identification of a portion of the non-volatile memory and adesignation for the portion of the memory. The portion of non-volatilememory may be a page of memory or multiple pages of memory. Thedesignation may then either be stored in a system file or in circuitryin the FPGA. The designation may indicate that the portion ofnon-volatile memory is read-only. If a portion of the memory isdesignated as read-only, the system is prevented from erasing orover-writing the portion of memory.

FIG. 2 illustrates a block diagram of an FPGA 800 that includes anon-volatile memory 830. FPGA 800 includes a programmable logic unit805, input/output (I/O) circuitry 810, a JTAG port 820, a TAP controllercircuit 825, a program/erase control circuit 815, and a UJTAG port 807.The programmable logic unit (PLU) 805 is a block of programmable logiccircuits comprised of programmable logic blocks or “tiles” and routinglines. PLU 805 may be, for example, a non-volatile programmable logicunit such as a flash-based FPGA block. Although the term “flash” oftenrefers to memories that are bulk erased on a page-by-page,sector-by-sector, or entire array basis, for the purposes of thisdisclosure “flash” refers to any electrically erasable {andre-programmable) non-volatile memory technology, regardless of theparticular erase scheme. Furthermore, although “flash” most commonlyrefers to memory devices comprised of floating-gate transistors, as usedin this disclosure, “flash” includes other non-volatile technologiesknown in the art such as, for example, SONOS, MONOS, siliconnanocrystal, ferro-electric, and solid-electrolyte switching devices. Inone embodiment, the programmable logic cells of programmable logic unit805 include non-volatile transistors of the same type as are used innonvolatile memory 830, for example, the non-volatile programmableelements employed in logic unit 805 and non-volatile memory 830 may becomprised of the same types of floating gate transistors.

I/O circuitry 810 is comprised of I/O pins and circuitry that providesconnections between an external system 860 and the programmable logicunit 805, for example via I/O tiles (dedicated I/O circuits) of theprogrammable logic unit (not shown). System 860 may be, for example,other electronic components residing on a circuit board with FPGA 800.JTAG port 820 is comprised of I/O pins and circuits (for example, thesame types of circuits as used in I/O 810) that are connected tohardwired circuits on the chip that implement all or part of the JTAGstandard (see Joint Test Action Group (JTAG) standard IEEE 1149.1 etseq.). The JTAG port 820 is connected to a TAP controller circuit 825.The TAP controller is a hardwired circuit, for example, a state machine,implementing some or all of the JTAG standard, including the Test AccessPort (TAP), and in some embodiments, additional functions implementedthrough device-specific control logic. The functionality of the TAPcontroller, including the state diagram, is governed by the JTAGstandard, and will not be repeated here to avoid overcomplicating thedisclosure. The TAP controller is connected to programming/accesscircuitry 815 and JTAG port 807. Programming/access circuitry 815 ishardwired circuitry that controls programming and erasing of theprogrammable elements in the programmable logic unit 805 andnon-volatile memory block 830 and also includes hardwired circuitrycontrolling access to the programmable logic unit 805 and non-volatilememory block 830. The programming/access circuitry 815 also controlsread operations and manages the signals and voltages required to programthe non-volatile memory block 830 and the programmable logic unit 805.The programming/access circuitry 815 may implement all or some of IEEEstandard 1532, which specifies how to use JTAG circuits and methods forprogramming.

JTAG port 820 connects to non-volatile programmable logic unit 805 viaTAP controller 825 and a user JTAG (UJTAG) port 807. UJTAG port 807 is aport to the programmable logic portion of the device through which auser may access the programmable logic via the JTAG port 820. UJTAG port807 is a hardwired circuit providing access to the programmable logicunit 805 for signals entering the device via the JTAG port 820. In oneembodiment, UJTAG port 807 is comprised of I/O tiles residing on theperiphery of the programmable logic unit 805. In another embodiment,UJTAG port 807 is comprised of portions of a group of I/O tiles, whilethe remainder of those I/O tiles is used for non-JTAG communication intoand out of the programmable logic unit 805. The UJTAG port 807 may bedefined, and its functionality implemented using decode logic 835. Thedecode logic 835 is shown in FIG. 2 as implemented in programmable logic(dashed line), however in other embodiments some or all of the decodelogic may be hardwired. An important aspect of the UJTAG port design isits connection with the TAP Controller 825 state machine.

As shown in FIG. 2, read, input, and output access to the programmablelogic unit 805 is provided to the user of the device via the JTAG port820, the TAP controller 825, and the UJTAG port 807 and decode logic835. Write access to the programmable logic unit 805 is provided to theuser of the device via the JTAG port 820, the TAP controller 825, andthe programming/access circuitry 815. Signals to/from the user and theexternal system to/from the programmable logic unit 805 may also beprovided via the regular I/O circuits 810 directly to the programmablelogic unit 805, for example via regular I/O tiles (not shown). As alsoshown in FIG. 2, read/write access to the non-volatile memory 830 isprovided to the user of the device via the JTAG port 820, the TAPcontroller 825, and the programming/access circuitry 815. Theprogrammable logic unit 805 has read access to the non-volatile memory,as shown in FIG. 2 and, consequently, read access to the non-volatilememory is also provided to the user through the programmable logic unit805, via regular 110 810.

The TAP controller 825 may be used as part of the program controlcircuitry for programming the programmable logic unit 805 of the device.Rather than just using the TAP controller circuitry for programming ofthe programmable logic, an embodiment of the present invention includesa bi-directional bus interface in the TAP controller so it can read andwrite data when it is not being used for programming the programmablelogic. Since the JTAG port 820 provides a user-accessible connection tooff chip devices, a user may access the non-volatile memory block 830and the programmable logic block 805, and the I/O circuitry of thedevice, all via the JTAG port.

In an exemplary embodiment, there is bidirectional access from the JTAGport to the programmable logic unit I/O tiles (not, shown) during normaloperation of the device. The UJTAG tiles 807 are directly connected tothe JTAG Test Access Port (TAP) Controller 825 in normal operating mode.As a result, functional blocks of the device architecture, such as aClock Conditioning Circuit (CCC) with a phase lock loop (PLL), I/Otiles, and SRAM blocks (not shown) can be reached via the JTAG port.

In one example, the UJTAG functionality is available by instantiating adecode logic macro in the configuration data of a design to instantiatethe decode logic 835. In one embodiment write access to the non-volatilememory 830 is only available to the user or the FPGA programmable logicunit 805 via the program/access circuitry 815 (the programmable logicunit 805 FPGA's direct access to the non-volatile memory 830 isread-only). In another embodiment, the programmable logic unit 805 hasdirect read/write access to the memory, without going through theprogram/access circuitry 815.

Bidirectional access to the JTAG port 820 from the programmable logicunit 805 creates flexibility to implement many different applicationsbased on importing/exporting data through the UJTAG port 807. DynamicReconfiguration of clock conditioning circuits (CCCs), which includePLL, can be performed dynamically through either an embedded shiftregister or static flash programming switches. These bits control thecharacteristics of a CCC: routing MUX architectures, delay values,divider values, etc. An embedded shift register (for the dynamicconfiguration of the CCC) is accessible to the programmable logic unit805, which, in turn, has access to the UJTAG tiles. Therefore, the CCCconfiguration shift register can receive and load the new configurationdata stream received via the JTAG port 820.

Dynamic reconfiguration eliminates the need to reprogram the device whenreconfiguration of the CCC functional blocks is needed. The CCCconfiguration can be modified while the device continues to operate. Theuser may be required to design a module to provide the configurationdata and control the CCC configuration shift register. In essence, thisis a user-designed TAP Controller requiring programmable logicresources.

In some applications, design constants or parameters need to be modifiedafter programming the original design. The tuning process can be doneusing the UJTAG port without reprogramming the device with new values.If the parameters or constants of a design are stored in distributedregisters or embedded SRAM memory blocks, the new values can be shiftedonto pins of the JTAG port dedicated to the TAP Controller 825,replacing the old values.

The UJTAG port 807 is used as the “bridge” for data transfer between theJTAG pins 820 (via the TAP controller 825) and the logic blocks of theprogrammable logic unit 805 or SRAM logic.

In many applications, the design needs to be tested, debugged, andverified on real silicon or in the final embedded application. In orderto debug and test the functionality of designs, users may need tomonitor some internal logic (or nets) during device operation. Theapproach of adding design test pins to monitor the critical internalsignals has many disadvantages, such as limiting the number of userI/Os. Furthermore, adding external I/Os for test purposes may requireadditional or dedicated board area for testing and debugging.

The UJTAG port 807 offers a flexible and cost-effective solution forsilicon test and debug applications. In this solution, the signals undertest are shifted out to the TAP Controller 825.

In one embodiment, all the test signals are monitored through the TAPcontroller 825—no pins or additional board-level resources are required.In some embodiments of the invention, a device includes embeddedvolatile memory (for example, an SRAM memory block). In one embodiment,users can initialize an embedded SRAM memory using the UJTAG port wherethe initialization data is imported using the TAP Controller. In anotherembodiment, similar functionality is available using the JTAG port.

The contents of the non-volatile memory block 830 are available to theprogrammable logic unit 805 during normal operation through a readoperation. As a result, the decode logic 835 can be used to provide thenonvolatile memory block 830 contents to the JTAG port during normaloperation.

The non-volatile memory block 830 read address can be provided fromoutside the device through an input or can be generated internally usingthe programmable logic unit 805. In either case, data serializationlogic may be used and can be designed using the logic of theprogrammable logic unit. Non-volatile memory contents may be readasynchronously in parallel from the non-volatile memory and shifted outin a synchronous serial format. The TAP state machine may be used tocoordinate a data shift procedure.

FIG. 3 illustrates a block diagram of selected components of an FPGA 800according to an embodiment of the present invention. FIG. 3 illustratesin more detail an example of a programmable logic unit 805. PLU 805includes programmable logic modules 110-113. Programmable logic modules110-113 each include programmable circuitry configurable to performlogic operations on received data. A description of the configuration ofthe circuitry in logic units is unnecessary to understand this inventionand is omitted for brevity.

Inputs and outputs of logic units 110 and 111 are connected to bus 120.In a programmable logic device, busses may be comprised of programmablerouting lines that are interconnected according to a user programdesign. Bus 120 includes routing lines 121-123 which each carry signals.The inputs and outputs of logic units 112 and 113 are connected to bus125. Bus 125 includes paths 126-128 which each carry a signal. Bus 135connects inputs/outputs 136 and 137. Bus 135 includes paths 138-140 thateach carry a signal. Bus 130 connects to busses 120, 125 and 135. Bus130 also connects to non-volatile memory 105. One skilled in the artwill recognize that each logic unit 110-113 may have separate inputs andoutputs connected to separate busses. However, the precise configurationof the circuitry of PLU 805 is not necessary to understand thisinvention and is omitted for brevity. The busses merely convey howcircuitry in PLU 805 may be configured.

Each junction, such as junction 150, at which a routing line in one bus120, 125, 130 intersects with a corresponding routing line in anotherbus 120, 125, and 130 includes a switch. By closing the properconfiguration of switches, any component of programmable logic unit 805may be connected to any other component of PLU 805. For non-volatilebased PLU's, once logic units are configured by loading configurationdata, the logic units do not need to have the configuration datare-loaded on subsequent power ups.

FIG. 4 shows an example of a system 860 of which an FPGA 800 may be apart. System 860 is controlled by a central processing unit (CPU) 201,which may be, for example, a microprocessor or microcontroller. CPU 201is connected to a read-only memory 211, and a random access memory 212.The memories connected to CPU 201 could be any kind of memory from asmall SRAM chip to a high-capacity hard disk drive. CPU 201 is alsoconnected to an I/O device 223, which may be any type of circuit ordevice that generates or receives signals, and may include an analog todigital or digital to analog converter. In one example, I/O device 223is a keyboard, a pointing device or other device that may be used by auser to input or output data. CPU 201 is also connected to FPGA 800, viathe JTAG port, as further described with reference to FIG. 3. CPU 201can control the programming and erasing of FPGA 800, including theprogrammable logic unit 805 and non-volatile memory 830.

FIG. 5 illustrates process 500 performed to load configuration data andstore user data into programmable logic unit 805 and non-volatile memory830, respectively, of FPGA 800. Process 500 begins with step 501, inwhich device data is written into a portion of the non-volatile memory.Device data may include, for example: device specific data such as aserial number, a date stamp, or an identifier; device type data such asa product identifier code, parameters for a particular function, orvalues of constants for certain applications performed by theprogrammable logic unit; and security data such as an encryption ordecryption key. Programming devices with unique serial numbers can helpmanufacturers, distributors, and users track devices and inventories.

In some embodiments of the invention, step 501 may include disablingcertain types of access to a portion of the non-volatile memory. Forexample, security bits not accessible to the user may be set to instructthe program/erase control circuitry to disable read, write, and eraseaccess to a portion of the non-volatile memory used by the manufacturer.This would prevent the user, or any other party, from accidentallyerasing or over-writing device data such as a serial number, calibrationdata, etc. Furthermore, it could be used to prevent the user or otherparty from reading security data such as an encryption or decryptionkey. In addition, security bits accessible to the user may be used bythe manufacturer or user to disable the capability to perform externalread/write functions on a portion of the non-volatile memory via theJTAG port. For example, the user may disable JTAG accessibility to aportion of the non-volatile memory after programming user data into thenon-volatile memory. Even where external access to the non-volatilememory is disabled, the programmable logic unit may be able to read thedata from the non-volatile memory through its read connection.

Step 501 may be performed by the device manufacturer or other (trusted)party before the device is sent to a customer or an unsecure environmentfor programming. For example, the user may send a device with a secureddecryption key along with an encrypted configuration data file to athird party programmer to program the device with the configuration datafile. In this case, the third party programmer need not be a trustedparty because the programmer will not have access to either thedecrypted configuration data file or the decryption key. Decryption ofconfiguration data may be done, for example, with hardwired circuitrysuch as an AES decryption block in the program/erase control circuitry.Decryption circuitry may also be programmed into the programmable logicunit for implementation of decryption functions by the user.

In step 505 configuration data is received for the programmable logicunit 805 portion of the FPGA 800. The configuration data may be storedin a file read from memory or may be received over a network connection.As stated above, configuration data is data that is applied to circuitryof programmable logic unit 805 to program selected programmable elementsto configure the programmable logic and routing to implement a user'slogic design.

In optional step 510, user data is received. As stated above, user datais data that is stored in non-volatile memory and conveys information ordefines parameters for performance of a function. User data may includedevice type data and device specific data. Device type data is data thatis common to all devices in a product family. Device type data includes,but is not limited to, specific parameters for a function, constants forfunctions, and other data that may describe the product family of FPGA800. Device specific data may include, but is not limited to, serialnumbers, date stamps and unique identifiers particular to a specificFPGA device, customer, or application. FIG. 6 is described below andshows a method for receiving the user data.

In optional step 515, security data is received. Step 515 wouldgenerally be performed when security data was not part of device datareceived in step 501, however, in some embodiments, additional securitydata may be received to secure different data (e.g., user data orconfiguration data) from the data secured by the security data providedin step 501. Security data is data that may be used to secure otherdata. In some embodiments, the security data may be an encryption ordecryption key that may be used to decrypt user data in FPGA 800, forexample using AES encryption/decryption or another knowencryption/decryption scheme. A memory file may be generated in optionalstep 520. The memory file may be a file storing user data and securitydata that may be stored to the non-volatile memory at one time. In someembodiments, the security data may be placed in a file and may be storedin the non-volatile memory prior to storing other data. The securitydata may then be used to decrypt other received data prior to storage oruse in programming.

The memory file may also be stored in a system memory of a processor forfuture use. Alternatively, the memory file may include the configurationdata and the user data or configuration, user, and security data. Inthese cases, it is preferable that the configuration data is easilyseparated from the user data for loading and/or editing.

In step 525, the configuration data is loaded into programmable logicunit 805 to configure the circuitry. For purposes of this discussion,circuitry of programmable logic unit 805 includes all logic units andinterconnections between the logic units in programmable logic unit 805.In step 530, the user data is stored in the non-volatile memory 830. Oneskilled in the art will recognize that steps may be preformed in adifferent order from what is shown in FIG. 4. For example, there may betime user and/or security data is stored in the non-volatile memoryprior to storing the configuration data. One particular example of thisis when security data is stored prior to other data for use indecrypting other data prior loading. After the configuration data isloaded and the user data is stored, process 500 ends.

In some embodiments, the user data is stored in a system memory of adevice that performs the loading of data. In these instances device typedata may be stored in a data file in the system memory. The devicespecific data may then be stored in a database having a separate recordfor each device. Process 600 illustrated in FIG. 6 is flow diagram of aprocess for receiving the user data in an exemplary embodiment. Process600 begins in step 605 by reading the device type data from the usermemory. This may include reading a data file storing the device typedata. In step 610, the device specific data is read. This may includereading a record for a particular device from a database. After step610, process 600 ends.

One advantage of a non-volatile memory is that certain portions of thememory may be protected or modified without affecting other portions ofthe memory. Furthermore, the path used to access portions of memoriesmay be restricted. In most flash memories, the memory is divided intopages. Process 300, illustrated in FIG. 7, takes advantage of this factto allow designation of portions of the memory to allow different usesof different portions. In a flash memory, a portion may be a page ofmemory or multiple pages of memory. Process 300 begins in step 305 byreceiving an identification of a portion of the non-volatile memory. Forexample, the identification may identify a page of the memory.

In step 310, a designation for the identified portion of memory isreceived. Some examples of designations, include but are not limited to,read-only, and read-write. Some other examples include the path that maybe used to access the memory. This may include limiting user access tothe JTAG port 820, to only accessing the non-volatile memory through theJTAG port 820, or through the I/O port 810 (via the programmable logicunit 805). Another example may include allowing programmable logic unit805 to read only through direct access and not to read/write throughprogram/access circuitry 815. In this case read/write access through theJTAG port may or may not be enabled. One skilled in the art willrecognize that designations may be used for other types of limitationsof the paths through which non-volatile memory 830 is accessed.

Access to the non-volatile memory from the JTAG port may be disabled forall or a portion of the memory so that the PLU can control all useraccess to the memory (e.g., make certain portions read-only). In step315, the designation is stored, this designation may be stored as partof a data file in system memory storing the user data or may be storedin the configuration logic of programmable logic unit 805. Process 300then ends.

While embodiments and applications of this invention have been shown anddescribed, it would be apparent to those skilled in the art that manymore modifications than mentioned above are possible without departingfrom the inventive concepts herein. The invention, therefore, is not tobe restricted except in the spirit of the appended claims.

1. A method for programming an integrated circuit including anon-volatile memory and a programmable logic unit, the methodcomprising: programming device data into a first portion of thenon-volatile memory; programming a user design into the programmablelogic unit; and programming user data into a second portion of thenon-volatile memory.
 2. The method of claim 1, wherein the device dataincludes a decryption key, further comprising: decrypting the user databefore programming the user data into the non-volatile memory.
 3. Themethod of claim 1, wherein the device data includes at least one of aserial number and a date code.
 4. The method of claim 1, furthercomprising: disabling write access to the first portion of thenon-volatile memory after programming device data into the first portionof the non-volatile memory.
 5. The method of claim 4, furthercomprising: disabling read access to the first portion of thenon-volatile memory after programming device data into the first portionof the non-volatile memory.
 6. The method of claim 1, wherein:programming user data into a second portion of the non-volatile memoryis performed via a TTAG port and a TAP controller circuit disposed onthe integrated circuit.
 7. A method for programming an integratedcircuit including a non-volatile memory and a programmable logic unit,the method comprising: receiving configuration data for programming theprogrammable logic unit; receiving user data for writing into thenon-volatile memory; programming the programmable logic unit with theconfiguration data; and writing the user data into the nonvolatilememory.
 8. The method of claim 7, further comprising: receiving anidentification of a portion of said non-volatile memory; receiving adesignation of said portion of said non-volatile memory; and storingsaid designation for said identified portion of memory.
 9. The method ofclaim 8, wherein the designation is read-only.
 10. The method of claim8, wherein the designation identifies a path through which theidentified portion of memory is accessed.
 11. The method of claim 10,wherein the path is a JTAG port.
 12. The method of claim 10, wherein thepath is through programmable logic.
 13. The method of claim 10, whereinidentification of the path limits access to the identified portion ofthe non-volatile memory to access only via the identified path.